The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Dec. 10, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Gary Peter Moscaluk, Colorado Springs, CO (US);

Bogdan I. Georgescu, Colorado Springs, CO (US);

Timothy Williams, Bellevue, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); H03K 17/0412 (2006.01); G11C 17/08 (2006.01); G11C 11/417 (2006.01); G11C 16/30 (2006.01); G11C 11/22 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 17/04123 (2013.01); G11C 11/2297 (2013.01); G11C 11/417 (2013.01); G11C 16/30 (2013.01); G11C 17/08 (2013.01); H03K 19/018507 (2013.01);
Abstract

A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.


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