The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Jul. 21, 2015
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Shozo Kanzaki, Tokyo, JP;

Fumiaki Arimai, Tokyo, JP;

Hiroyoshi Nishizaki, Tokyo, JP;

Masato Nakanishi, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/28 (2006.01); H05K 1/09 (2006.01); H01R 12/72 (2011.01); H05K 1/02 (2006.01); H01R 13/03 (2006.01); H01R 13/52 (2006.01); H01R 24/60 (2011.01);
U.S. Cl.
CPC ...
H01R 12/721 (2013.01); H01R 13/03 (2013.01); H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 3/28 (2013.01); H01R 13/5216 (2013.01); H01R 24/60 (2013.01); H05K 2203/1327 (2013.01);
Abstract

An electronic equipment unit includes a multi-layer circuit board. A part arrangement region on which circuit parts are mounted and a terminal region are provided on the multi-layer circuit board. The part arrangement region is encapsulated with resin. An outline region is formed from a solder resist film surrounding the part arrangement region to prevent the resin from flowing into the terminal region. A non-solder resist region is provided so as to surround the outline region and formation of the solder resist film is inhibited in the non-solder resist region. A clamp abutting surface which is pressed by a mold and surrounds the terminal region and thereby prevents the resin from flowing into the terminal region is a partial region of the multi-layer circuit board where a surface layer circuit pattern is absent.


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