The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Jan. 30, 2015
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Yuji Egi, Isehara, JP;

Hideomi Suzawa, Atsugi, JP;

Shinya Sasagawa, Atsugi, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 27/146 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 27/127 (2013.01); H01L 27/14616 (2013.01); H01L 29/0684 (2013.01); H01L 29/78603 (2013.01); H01L 29/78693 (2013.01); H01L 21/02565 (2013.01); H01L 27/1225 (2013.01);
Abstract

In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.


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