The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2017
Filed:
Aug. 25, 2015
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Mikio Tsujiuchi, Tokyo, JP;
Kouji Tanaka, Tokyo, JP;
Yasuki Yoshihisa, Tokyo, JP;
Shunji Kubo, Tokyo, JP;
Assignee:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 29/0847 (2013.01); H01L 29/0873 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/4175 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 21/26586 (2013.01); H01L 29/0653 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01);
Abstract
A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an ndrain region toward an nsource region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the ndrain region toward the nsource region.