The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Mar. 05, 2015
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Ahmet S. Ozcan, Grenoble, FR;

Emmanuel Petitprez, Grenoble, FR;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/42364 (2013.01); H01L 29/51 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/66628 (2013.01); H01L 29/7838 (2013.01); H01L 29/665 (2013.01);
Abstract

An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.


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