The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2017
Filed:
Oct. 22, 2013
Applicant:
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;
Inventors:
Haizhou Yin, Poughkeepsie, NY (US);
Rui Li, Beijing, CN;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 29/0649 (2013.01); H01L 29/6653 (2013.01); H01L 29/66636 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01);
Abstract
Provided is a MOSFET, comprising: a substrate (); a gate stack () on the substrate (); source/drain regions () in the substrate on both sides of the gate stack (); an interlayer dielectric layer () covering the source/drain regions; and source/drain extension regions () under edges on both sides of the gate stack (); wherein insulators, which are not connected each other, are formed beneath the source/drain extension regions () under edges on both sides of the gate stack (). By means of the MOSFET in the present disclosure, negative effects induced by DIBL on device performance can be effectively reduced.