The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

May. 19, 2016
Applicants:

Gwang-hyun Baek, Seoul, KR;

Inho Kim, Suwon-si, KR;

Jong-kyu Kim, Seongnam-si, KR;

Jongchul Park, Seongnam-si, KR;

Jung-ik OH, Hwaseong-si, KR;

Inventors:

Gwang-Hyun Baek, Seoul, KR;

Inho Kim, Suwon-si, KR;

Jong-Kyu Kim, Seongnam-si, KR;

Jongchul Park, Seongnam-si, KR;

Jung-Ik Oh, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/10 (2006.01); G11C 11/16 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); H01L 23/528 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01);
Abstract

A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.


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