The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2017
Filed:
Apr. 05, 2013
Applicant:
Ams Ag, Unterpremstaetten, AT;
Inventors:
Assignee:
AMS AG, Unterpremstaetten, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01); H01L 31/0296 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1469 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 31/0296 (2013.01); H01L 27/14661 (2013.01); H01L 2924/14 (2013.01); H01L 2924/37001 (2013.01);
Abstract
The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (), a further semiconductor wafer (), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer () arranged on the further semiconductor wafer () and a metal layer connecting the contact layer with an integrated circuit.