The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Apr. 21, 2015
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Masatsugu Itahashi, Yokohama, JP;

Seiichi Tamura, Yokohama, JP;

Nobuaki Kakinuma, Tokyo, JP;

Mineo Shimotsusa, Machida, JP;

Masato Fujita, Kitakyushu, JP;

Yusuke Onuki, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H01L 27/146 (2006.01); H01L 27/148 (2006.01); H04N 5/374 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14689 (2013.01); H01L 27/1461 (2013.01); H01L 27/1462 (2013.01); H01L 27/1463 (2013.01); H01L 27/14614 (2013.01); H01L 27/14616 (2013.01); H01L 27/14812 (2013.01); H04N 5/374 (2013.01);
Abstract

A solid-state image sensor includes a pixel area and a peripheral circuit area. The pixel area includes a first MOS, and the peripheral circuit area includes a second MOS. A method includes forming a gate of the first MOS and a gate of the second MOS, forming a first insulating film to cover the gates of the first and second MOSs, etching the first insulating film in the peripheral circuit area in a state that the pixel area is masked to form a side spacer on a side face of the gate of the second MOS, etching the first insulating film in the pixel area in a state that the peripheral circuit area is masked, and forming the second insulating film to cover the gates of the first and second MOSs and the side spacers.


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