The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

May. 04, 2016
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Yuichi Nakao, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/11507 (2017.01); H01L 21/768 (2006.01); H01L 27/11504 (2017.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11507 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02266 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01); H01L 21/32 (2013.01); H01L 21/7687 (2013.01); H01L 21/76849 (2013.01); H01L 27/11504 (2013.01); H01L 28/55 (2013.01); H01L 28/57 (2013.01); H01L 28/82 (2013.01);
Abstract

A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.


Find Patent Forward Citations

Loading…