The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Dec. 22, 2015
Applicant:

Inotera Memories, Inc., Taoyuan, TW;

Inventor:

Shing-Yih Shih, New Taipei, TW;

Assignee:

INOTERA MEMORIES, INC., Taoyuan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3157 (2013.01); H01L 23/552 (2013.01); H01L 24/02 (2013.01); H01L 2224/02372 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06544 (2013.01);
Abstract

A multi-chip semiconductor package includes a lower RDL interposer, a first chip on the lower RDL interposer within a chip mounting area, via components mounted within a peripheral area, and a first molding compound surrounding the first chip and the via components. Each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion. An upper RDL interposer is integrally constructed on the first chip, on the via components, and on the first molding compound. The upper RDL interposer is electrically connected to the connection portion of each of the via components. A second chip is mounted on the upper RDL interposer. A second molding compound surrounds the second chip.


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