The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Jan. 28, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Kentaro Saito, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/74 (2006.01); H01L 21/78 (2006.01); H01L 23/58 (2006.01); H01L 23/10 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 24/49 (2013.01); H01L 21/743 (2013.01); H01L 21/78 (2013.01); H01L 23/10 (2013.01); H01L 23/3157 (2013.01); H01L 23/585 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/48 (2013.01); H01L 23/3107 (2013.01); H01L 23/3192 (2013.01); H01L 23/522 (2013.01); H01L 23/562 (2013.01); H01L 24/45 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/02235 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/03827 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/06179 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48177 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/48624 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including a first pad, arranged along the second side and formed over a semiconductor substrate. The first pad is arranged nearer the corner than other pads of the plurality of pads. The first pad includes a third side, a fourth side being perpendicular to the third side, a fifth side being parallel to the third side and a sixth side being perpendicular to a fifth side. The third side and the fourth side are nearer to the corner than the fifth side and sixth side. A first dummy wiring is formed along the first side. A second dummy wiring is formed along the second side. The first dummy wiring and the second dummy wiring are formed integrally with each other.


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