The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Apr. 26, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Kyeong Min Chae, Seoul, KR;

Min Su Kim, Busan, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 11/5628 (2013.01);
Abstract

A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.


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