The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Aug. 26, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventor:

Yukihiro Fujimoto, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01); H01L 27/11 (2006.01); G11C 5/02 (2006.01); G11C 8/08 (2006.01); G11C 11/417 (2006.01); G11C 11/41 (2006.01); G11C 29/04 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/025 (2013.01); G11C 8/08 (2013.01); G11C 11/417 (2013.01); G11C 11/418 (2013.01); H01L 27/1116 (2013.01); G11C 11/41 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/1804 (2013.01);
Abstract

A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on the data path circuits and control circuits. Each of data path circuits includes a memory cells disposed in rows along the first direction and columns along a second direction crossing the first direction and a read/write circuit disposed at an end of the columns of memory cells. At least one pair of adjacent columns of memory cells has an electrical separation between the gate polysilicon layer the pair of adjacent memory cell columns—that is, gate conductor layer of the adjacent memory columns are electrically distinct. A word line in the first metal layer is segmented along the first direction into separately addressable portions.


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