The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Nov. 04, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventor:

Koji Kohara, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 11/419 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes first, second, third and fourth MOS transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth MOS transistors. Source and drain of the third MOS transistor are connected to between the source or the drain of the first MOS transistor and a first bit line. Source and drain of the fourth MOS transistor are connected to between the source or the drain of the second MOS transistor and a second bit line. The first precharge circuit supplies a voltage to the first and second bit lines in a precharge period during a read operation or a write operation. The second precharge circuit supplies the voltage to the first and second bit lines while in a data holding state.


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