The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2017
Filed:
Mar. 20, 2014
Xyratex Technology Limited, Havant, Hampshire, GB;
Eugene Mathew Taranta, II, Casselberry, FL (US);
XYRATEX TECHNOLOGY LIMITED, Havant, GB;
Abstract
Method of defining a layout mapping function for a parity distributed RAID array including target objects, the layout mapping function defining the mapping of the stripe group-address space to the target-address space in the array and including a matrix defining a unit space across target objects, the matrix includes columns defining the objects and rows defining equally-offset sequential units on the objects, the method including: specifying P target objects, where P>1; b) specifying A target objects as spare space, where A<P and A≧1; defining a sub-matrix of P' columns, where P′=P−A; defining a layout of stripe groups across the P′ target objects in the sub-matrix, each stripe group comprising data units and parity units; adding A columns, representative of the A spare space target objects, to the sub-matrix to form a complete matrix defining the layout mapping function; and implementing the layout mapping function on the objects.