The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Dec. 17, 2013
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventor:

Zixiong Wang, Ottawa, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/44 (2006.01); H04L 12/745 (2013.01); H04L 12/743 (2013.01); H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
H04L 45/748 (2013.01); H04L 45/741 (2013.01); H04L 45/7457 (2013.01);
Abstract

A trie comprising a plurality of subtries may be balanced by storing, in a first memory stage, a first root that identifies a first subtrie of a trie and a second root that identifies a second subtrie, which is a direct or indirect child of the first subtrie. A plurality of network address prefixes representing vertexes in the plurality of subtries may be stored in at least one additional memory stage. As the first subtrie is located on a top subtrie level which may contain relatively fewer network address prefixes, promoting the second subtrie to the top subtrie level may help improve memory utilization. Further, looking up any received network address may have less memory access latency.


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