The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Mar. 04, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Atsushi Honda, Setagaya, JP;

Yoji Ohashi, Fucyu, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04K 1/02 (2006.01); H04L 25/03 (2006.01); H04L 25/49 (2006.01); H04B 7/06 (2006.01); H01Q 3/26 (2006.01); H03F 1/02 (2006.01); H03F 3/19 (2006.01); H03F 3/21 (2006.01); H03F 3/24 (2006.01); H03F 3/72 (2006.01); H03G 3/30 (2006.01); H03H 11/34 (2006.01); H04B 1/40 (2015.01); H04L 5/00 (2006.01);
U.S. Cl.
CPC ...
H04B 7/0667 (2013.01); H01Q 3/26 (2013.01); H03F 1/0277 (2013.01); H03F 3/19 (2013.01); H03F 3/211 (2013.01); H03F 3/245 (2013.01); H03F 3/72 (2013.01); H03G 3/3042 (2013.01); H03G 3/3084 (2013.01); H03H 11/34 (2013.01); H04B 1/40 (2013.01); H04L 5/006 (2013.01); H03F 2200/451 (2013.01); H03F 2203/21112 (2013.01);
Abstract

A wireless communication device includes a delay circuit to generate four or more delay signals, an amplifier circuit amplifying the four or more delay signals to generate four or more amplified delay signals, and a combiner circuit combining at least two amplified delay signals to generate an output signal, a second phase of a second amplified delay signal is between a first phase of a first amplified delay signal and a third phase of a third amplified delay signal, gains of the amplifier circuit for the four or more delay signals are controlled such that the output signal is generated by combining the first amplified delay signal and the third amplified delay signal, and a phase of the output signal is between the first phase of the first amplified delay signal and the third phase of the third amplified delay signal.


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