The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Sep. 14, 2015
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Michael Pelissier, Grenoble, FR;

Anton Korniienko, Lyons, FR;

Mykhailo Zarudniev, Kiev, UA;

Gèrard Scorletti, Ecully, FR;

Olesia Mokrenko, Grenoble, FR;

Eric Blanco, Decines-Charpieu, FR;

Patrick Villard, Grenoble, FR;

Gèrard Billiot, Saint-Nazaire les Eymes, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/097 (2006.01); H03L 7/08 (2006.01); G06F 17/50 (2006.01); H04L 7/00 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/097 (2013.01); G06F 17/5045 (2013.01); H03L 7/08 (2013.01); H04L 7/0079 (2013.01); H03L 7/099 (2013.01); H03L 2207/50 (2013.01);
Abstract

A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.


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