The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Mar. 20, 2014
Applicant:

Optis Circuit Technology, Llc, Plano, TX (US);

Inventor:

Vincent Knopik, St. Pierre d'Allevard, FR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 3/19 (2006.01); H03F 3/24 (2006.01); H03F 3/193 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0222 (2013.01); H03F 1/0266 (2013.01); H03F 1/223 (2013.01); H03F 3/19 (2013.01); H03F 3/193 (2013.01); H03F 3/245 (2013.01); H03F 2200/102 (2013.01); H03F 2200/108 (2013.01); H03F 2200/15 (2013.01); H03F 2200/18 (2013.01); H03F 2200/451 (2013.01);
Abstract

An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.


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