The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Nov. 26, 2013
Applicant:

University of Florida Research Foundation, Inc., Gainesville, FL (US);

Inventors:

Andrew Gabriel Rinzler, Newberry, FL (US);

Bo Liu, Gainesville, FL (US);

Mitchell Austin McCarthy, Gainesville, FL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/05 (2006.01); H01L 27/28 (2006.01); H01L 51/10 (2006.01); H01L 29/739 (2006.01); B82Y 10/00 (2011.01); H01L 29/16 (2006.01); H01L 29/41 (2006.01); H01L 27/092 (2006.01); H01L 51/00 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 51/057 (2013.01); B82Y 10/00 (2013.01); H01L 27/092 (2013.01); H01L 27/283 (2013.01); H01L 29/1606 (2013.01); H01L 29/413 (2013.01); H01L 29/7395 (2013.01); H01L 51/0566 (2013.01); H01L 51/102 (2013.01); H01L 29/0673 (2013.01); H01L 29/775 (2013.01); H01L 51/0039 (2013.01); H01L 51/0047 (2013.01); H01L 51/0048 (2013.01); H01L 51/105 (2013.01);
Abstract

Various examples are provided for ambipolar vertical field effect transistors (VFETs). In one example, among others, an ambipolar VFET includes a gate layer; a source layer that is electrically percolating and perforated; a dielectric layer; a drain layer; and a semiconducting channel layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric layer and the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. Another example includes an ambipolar vertical field effect transistor including a dielectric surface treatment layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric surface treatment layer and where the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier.


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