The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Apr. 16, 2014
Applicant:
SK Hynix Inc., Icheon, KR;
Inventor:
Jung Tae Jeong, Icheon, KR;
Assignee:
SK HYNIX INC., Icheon, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/56 (2013.01); H01L 23/562 (2013.01); H01L 25/0655 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1076 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.