The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Jun. 06, 2016
Applicant:

The United States of America As Represented BY the Secretary of the Navy, Washington, DC (US);

Inventors:

Matthew Kay, Jasper, IN (US);

James David Ingalls, Bedford, IN (US);

Matthew Gadlage, Bloomington, IN (US);

Adam Duncan, Bloomington, IN (US);

Andrew Howard, Bloomington, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 5/00 (2006.01); G11C 29/50 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G11C 5/005 (2013.01); G11C 16/0408 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5002 (2013.01);
Abstract

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.


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