The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Oct. 27, 2014
Applicants:
Jintaek Park, Hwaseong-si, KR;
Youngwoo Park, Seoul, KR;
Jaeduk Lee, Seongam-si, KR;
Inventors:
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 27/115 (2017.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0466 (2013.01); G11C 5/02 (2013.01); G11C 16/10 (2013.01); H01L 27/0688 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 27/092 (2013.01);
Abstract
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.