The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Aug. 30, 2013
Applicant:

Southeast University, Jiangsu, CN;

Inventors:

Weiwei Shan, Jiangsu, CN;

Chaoxuan Tian, Jiangsu, CN;

Huafang Sun, Jiangsu, CN;

Longxing Shi, Jiangsu, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 11/30 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2035 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01); G06F 11/3024 (2013.01); G06F 11/3093 (2013.01); G06F 2201/805 (2013.01); G06F 2201/85 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1285 (2013.01);
Abstract

Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (), an error signal statistics module (), a voltage frequency control module (), an error recovery control module (), an in-situ error recovery module () and an upper-layer error recovery module (), wherein each of the on-chip monitoring circuits () is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.


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