The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Jun. 11, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Timothy J. Dell, Colchester, VT (US);

Girisankar Paulraj, Bangalore, IN;

Diyanesh B.Chinnakkonda Vidyapoornachary, Bangalore, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 3/06 (2006.01); G06F 11/20 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0683 (2013.01); G06F 11/2094 (2013.01); G06F 11/1666 (2013.01); G06F 11/20 (2013.01);
Abstract

According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.


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