The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Nov. 25, 2014
Applicants:

Globalfoundries Inc., Grand Cayman, KY (US);

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Suresh Uppal, Clifton Park, NY (US);

Andreas Kerber, Mount Kisco, NY (US);

William McMahon, Scarsdale, NY (US);

Eduard A. Cartier, New York, NY (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/14 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/14 (2013.01); G01R 31/2879 (2013.01);
Abstract

At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.


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