The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Aug. 21, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Bernhard Winkler, Regensburg, DE;

Andreas Zankl, Wiesent, DE;

Klemens Pruegl, Regensburg, DE;

Stefan Kolb, Unterschleissheim, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); H01L 27/06 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/008 (2013.01); B81C 1/00246 (2013.01); H01L 27/0611 (2013.01); B81B 2201/0264 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/015 (2013.01); B81C 1/00158 (2013.01); B81C 2203/0707 (2013.01); B81C 2203/0714 (2013.01); B81C 2203/0735 (2013.01); B81C 2203/0771 (2013.01);
Abstract

Embodiments relate to MEMS devices and methods for manufacturing MEMS devices. In one embodiment, the manufacturing includes forming a monocrystalline sacrificial layer on a non-silicon-on-insulator (non-SOI) substrate, patterning the monocrystalline sacrificial layer such that the monocrystalline sacrificial layer remains in a first portion and is removed in a second portion lateral to the first portion; depositing a first silicon layer, the first silicon layer deposited on the remaining monocrystalline sacrificial layer and further lateral to the first portion; removing at least a portion of the monocrystalline sacrificial layer via at least one release aperture in the first silicon layer to form a cavity and sealing the cavity.


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