The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Jun. 16, 2014
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Bogdan Govoreanu, Hulshout, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/12 (2013.01); G11C 13/0002 (2013.01); H01L 27/2418 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01);
Abstract

The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (k), a conduction band offset (Φ), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.


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