The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Jun. 13, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventor:

Teruyuki Mine, Yokkaichi, JP;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 21/768 (2013.01); H01L 21/823487 (2013.01); H01L 27/101 (2013.01); H01L 27/2454 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01); G11C 2013/009 (2013.01); G11C 2213/71 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01);
Abstract

A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the three-dimensional memory structure includes forming one or two channels in a transistor body to provide a current to selected memory cells. Programming can initially use one channel and subsequently use two channels based on a programming progress. A method for fabricating a semiconductor device includes etching a gate conductor material so that shared and non-shared control gates have a common height.


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