The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Mar. 18, 2014
Applicant:

Mcube, Inc., San Jose, CA (US);

Inventor:

Xiao (Charles) Yang, Cupertino, CA (US);

Assignee:

mCube Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/036 (2006.01); H01L 21/8238 (2006.01); G01L 9/00 (2006.01); H01L 21/762 (2006.01); H01L 27/06 (2006.01); H03H 3/007 (2006.01); G01P 15/125 (2006.01); G01P 15/08 (2006.01); H01L 21/822 (2006.01); B81C 1/00 (2006.01); H01L 29/04 (2006.01); H01L 25/065 (2006.01); A61B 5/145 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823878 (2013.01); B81C 1/00246 (2013.01); G01L 9/0042 (2013.01); G01L 9/0054 (2013.01); G01P 15/0802 (2013.01); G01P 15/125 (2013.01); H01L 21/76254 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H03H 3/0073 (2013.01); A61B 5/14514 (2013.01); B81B 2201/025 (2013.01); B81B 2201/055 (2013.01); H01L 25/0657 (2013.01); H01L 29/045 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.


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