The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Feb. 05, 2015
Applicants:

Dong-wook Seo, Hwaseong-si, KR;

Jae-seung Choi, Suwon-si, KR;

Hyun-su Choi, Suwon-si, KR;

Inventors:

Dong-Wook Seo, Hwaseong-si, KR;

Jae-Seung Choi, Suwon-si, KR;

Hyun-Su Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/22 (2013.01); G11C 5/14 (2013.01);
Abstract

A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.


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