The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2017
Filed:
Dec. 04, 2015
International Business Machines Corporation, Armonk, NY (US);
Alexander Fritsch, Esslingen, DE;
Ulrich Krauch, Dettenhausen, DE;
Michael B. Kugel, Boeblingen, DE;
Juergen Pille, Stuttgart, DE;
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
The invention relates to a current sense amplifier () comprising a reference current input terminal (), a sense control line input terminal (), a sense current input terminal (), a first output terminal (), and a second output terminal (). The amplifier further comprises a first NAND gate () comprising an output terminal being connected to the first output terminal (), a second NAND gate () comprising an output terminal being connected to the second output terminal (), a first (T, T) and a second (T, T) cross coupled inverters, the first inverter comprising a first n-FET (T) and the second inverter comprising a second n-FET (T), a transmission gate () comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to the sense control line input terminal (), an AND gate () having a first input terminal connected to the first output terminal () and a second input terminal connected to the second output terminal (), a third n-FET (T) having a gate connected to an output terminal of the AND gate (), a drain connected to the sense current input terminal, a source connected to ground, wherein a source of the first n-FET is connected to the sense current input terminal and a source of the second n-FET is connected to the reference current input terminal, a first input terminal of the first NAND gate and a first input terminal of the second NAND gate are connected to the sense control line input terminal, the first transmission terminal and a second input terminal of the first NAND gate are connected to an output terminal of the second inverter and the second transmission terminal and a second input terminal of the second NAND gate are connected to an output terminal of the first inverter.