The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Oct. 21, 2013
Applicant:

Xmos Limited, Bristol, GB;

Inventors:

Andrew Stanford-Jason, Salisbury, GB;

Michael David May, Bristol, GB;

Nigel Jürgen Toon, Bristol, GB;

Daniel John Pelham Wilkinson, Bristol, GB;

Assignee:

Xmos Limited, Bristol, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/24 (2006.01); G06F 15/173 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4286 (2013.01); G06F 9/3009 (2013.01); G06F 9/30072 (2013.01); G06F 9/30087 (2013.01); G06F 9/30123 (2013.01); G06F 9/3851 (2013.01); G06F 13/24 (2013.01); G06F 15/17356 (2013.01);
Abstract

A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.


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