The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Mar. 04, 2014
Applicants:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Toshiba Solutions Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Toshihiro Kikuchi, Tokyo, JP;

Naoki Iketani, Tokyo, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 17/30 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0634 (2013.01); G06F 3/0643 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 12/0692 (2013.01); G06F 17/30082 (2013.01); G06F 17/30091 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/222 (2013.01); G06F 2212/657 (2013.01);
Abstract

According to one embodiment, a storage controller includes a mode switching unit, a data input/output controller and a data arrangement controller. The mode switching unit switches a first mode to a second mode in accordance with a mode switching request from a host device based on a tier arrangement rule. The data input/output controller accesses a first sequence of blocks constituting a first file indicated by a tier arrangement rule, when the host device requests access to a logical address range storing the first sequence of blocks. The data arrangement controller transfers, to a storage area of a tier designated by the tier arrangement rule, data in an extent including a sequence of blocks located in a logical address range accessed in the second mode.


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