The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Mar. 07, 2014
Applicant:

Murata Manufacturing Co., Ltd., Kyoto-fu, JP;

Inventor:

Masaaki Mizushiro, Kyoto-fu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01); H01L 23/48 (2006.01); H01L 25/04 (2014.01); H01L 25/18 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0296 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/00 (2013.01); H01L 23/12 (2013.01); H01L 23/3121 (2013.01); H01L 23/48 (2013.01); H01L 23/49811 (2013.01); H01L 23/52 (2013.01); H01L 25/04 (2013.01); H01L 25/18 (2013.01); H05K 1/185 (2013.01); H01L 24/16 (2013.01); H01L 2224/0558 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01);
Abstract

To provide a module board capable of suppressing depression of a top face of insulating resin near the center of a substrate by arranging multiple columnar connection terminals not only on a peripheral area of the substrate but also between multiple electronic components that are mounted. Multiple electronic componentsandare mounted on one face of a substrateand the multiple electronic componentsandare sealed with insulating resin. Multiple columnar connection terminalsandare arranged on a peripheral area of the substrateand in one or more small areason the substrate, respectively. The one or more small areasare set at positions on the substrate, which is not on the peripheral area of the substrateand on which the multiple electronic componentsandare not mounted.


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