The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Jul. 31, 2014
Spansion Llc, Sunnyvale, CA (US);
Makoto Yashiki, Aichi, JP;
Toru Miyamae, Aichi, JP;
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided. A control apparatus for a buck-boost power supply comprises: a pulse-width modulation (PWM) signal generator configured to generate a PWM signal having a pulse whose pulse width is based on an output voltage; a mode pulse signal generator configured to generate a mode pulse signal having a signal whose time period is based on at least one of an input voltage, a difference between an input voltage and the output voltage, and a difference between an input voltage and a voltage proportional to the output voltage; a first delayed signal generator configured to generate a first delayed signal having a pulse whose rising edge or falling edge is delayed for a first delay time from a rising edge or a falling edge of the pulse of the PWM signal; and an output controller configured to control an output part of the buck-boost power supply, based on the PWM signal, the mode pulse signal, and the first delayed signal, the output part comprising: two primary switches that are each an N-type transistor; a boost capacitor for driving the high-side switch of the primary switches; and two secondary switches that are each a transistor, wherein the output controller controls switching of the output part so that a first time period during which the high-side switch of the primary switches is off and the low-side switch of the primary switches is on is longer than or equal to the first delay time.