The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Aug. 22, 2014
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Adrian Finney, Villach, AT;

Paolo Del Croce, Villach, AT;

Luca Petruzzi, Goedersdorf, AT;

Norbert Krischke, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 27/0629 (2013.01); H01L 27/0922 (2013.01); H01L 29/0607 (2013.01); H01L 29/0688 (2013.01); H01L 29/7805 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01);
Abstract

According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.


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