The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Nov. 13, 2014
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Wolfgang Werner, Munich, DE;

Frank Kahlmann, Neubiberg, DE;

Franz Hirler, Isen, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/43 (2006.01); H01L 29/06 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 29/0623 (2013.01); H01L 29/0657 (2013.01); H01L 29/205 (2013.01); H01L 29/407 (2013.01); H01L 29/43 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/0634 (2013.01); H01L 29/0843 (2013.01); H01L 29/2003 (2013.01); H01L 29/42316 (2013.01);
Abstract

A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.


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