The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Aug. 01, 2014
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Jinbiao Liu, Beijing, CN;

Yao Wang, Beijing, CN;

Guilei Wang, Beijing, CN;

Tao Yang, Beijing, CN;

Qing Liu, Beijing, CN;

Junfeng Li, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/265 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 29/0847 (2013.01); H01L 29/785 (2013.01);
Abstract

A method for manufacturing a FinFET device, including providing a substrate; implementing a source/drain doping on the substrate; etching the doped substrate to form a source region and a drain region; forming a fin channel between the source region and the drain region; and forming a gate on the Fin channel. The fin and the gate are formed after the source/drain doping is implemented on the substrate, so that the source/drain doping is done as a doping for a planar device, which ensures the quality of the source/drain coping and improves the property of the FinFET device.


Find Patent Forward Citations

Loading…