The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Jul. 31, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yeon-Tack Ryu, Yongin-si, KR;

Ho-Young Kim, Seongnam-si, KR;

Myoung-Hwan Oh, Hwaseong-si, KR;

Bo-Un Yoon, Seoul, KR;

Jun-Hwan Yim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/76829 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 21/823437 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01);
Abstract

Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.


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