The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Jan. 29, 2016
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Do-Hyun Kim, Seongnam-si, KR;

Yoon Ho Khang, Yongin-si, KR;

Dong-Hoon Lee, Seoul, KR;

Sang Ho Park, Suwon-si, KR;

Se Hwan Yu, Seoul, KR;

Cheol Kyu Kim, Seoul, KR;

Yong-Su Lee, Hwaseong-si, KR;

Sung Haeng Cho, Cheongwon-gun, KR;

Chong Sup Chang, Hwaseong-si, KR;

Dong Jo Kim, Yongin-si, KR;

Jung Kyu Lee, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1288 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1237 (2013.01); H01L 27/1262 (2013.01); H01L 29/45 (2013.01); H01L 29/7869 (2013.01);
Abstract

A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.


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