The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Dec. 30, 2015
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Hyeon Jun Lee, Hwaseong-si, KR;

Katsumi Abe, Ansan-si, KR;

Young-Wook Lee, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 21/563 (2013.01); H01L 21/76802 (2013.01); H01L 21/76879 (2013.01); H01L 23/3171 (2013.01); H01L 23/528 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.


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