The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Sep. 12, 2016
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chia-Chiuan Chang, Jhunan Township, TW;

Jui-Lung Chen, Hsinchu, TW;

Yu-Wen Chen, Jhubei, TW;

Hsuan-Chi Su, Taoyuan, TW;

Ching-Hsiang Lin, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); H01L 27/112 (2006.01); H01L 29/78 (2006.01); H01L 23/525 (2006.01); H01L 29/10 (2006.01); G11C 17/18 (2006.01); G11C 17/12 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/5252 (2013.01); H01L 27/11293 (2013.01); H01L 29/1083 (2013.01); H01L 29/7833 (2013.01); G11C 17/12 (2013.01); G11C 17/165 (2013.01); G11C 2213/79 (2013.01); H01L 23/5228 (2013.01); H01L 29/1033 (2013.01);
Abstract

An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.


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