The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Mar. 15, 2016
International Business Machines Corporation, Armonk, NY (US);
Karl R. Erickson, Rochester, MN (US);
Robert E. Kilker, Rochester, MN (US);
Phil C. Paone, Rochester, MN (US);
David P. Paulsen, Inver Grove Heights, MN (US);
Gregory J. Uhlmann, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A circuit has a wordline with an NVM element utilizing a first FET coupled to bitline true and a second FET coupled to bitline complement. A NFET coupled to the bitline complement is configured to pull bitline true toward ground in response to bitline complement reaching a first voltage. One or more wordline drivers are coupled to the NVM element such that a first path from a wordline driver is coupled to the first FET while a second path from a wordline driver is coupled to the second FET. The first path is current-limited in comparison to the second path, such that a first slew rate between a wordline driver and the first FET is slower than a second slew rate between a wordline driver and the second FET. The slew rate disparity allows the bitline complement to reach the first voltage.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile