The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Oct. 15, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Min Su Kim, Busan, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 16/06 (2006.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1039 (2013.01); G11C 7/1072 (2013.01); G11C 7/1087 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01);
Abstract

A semiconductor memory device includes a first page buffer block and a second page buffer block corresponding to a first memory bank and a second memory bank, respectively, an input/output control circuit suitable for transferring input data to data lines, a first column decoder and a second column decoder suitable for latching the input data transferred through the data lines to the first page buffer block and the second page buffer block, respectively, based on a column address transferred through address lines that are shared by the first and second column decoders, and a control signal generation circuit suitable for generating a plurality of page buffer selection signals to control the first and second column decoders to selectively perform data latch operations on the first and second page buffer blocks.


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