The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Jan. 12, 2016
Applicant:
Integrated Device Technology, Inc., San Jose, CA (US);
Inventors:
HaiQi Liu, Shanghai, CN;
Yue Yu, Johns Creek, GA (US);
Yumin Zhang, Shanghai, CN;
Yi Xie, Shanghai, CN;
Assignee:
Integrated Device Technology, inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 11/4093 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 7/1006 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); G11C 7/22 (2013.01); G11C 11/4093 (2013.01); G11C 7/1072 (2013.01);
Abstract
An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.