The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Mar. 08, 2016
International Business Machines Corporation, Armonk, NY (US);
Raphael Peter Robertazzi, Yorktown Heights, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n−1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n−1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n−1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n−1 and said layer n.