The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Mar. 29, 2012
Applicants:

Ayumu Tateoka, Saitama, JP;

Shinichi Obata, Saitama, JP;

Toshiyuki Shimizu, Saitama, JP;

Inventors:

Ayumu Tateoka, Saitama, JP;

Shinichi Obata, Saitama, JP;

Toshiyuki Shimizu, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 3/46 (2006.01); H05K 3/02 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4652 (2013.01); H05K 3/022 (2013.01); H05K 3/4658 (2013.01); H05K 3/4682 (2013.01); Y10T 29/49155 (2015.01);
Abstract

A manufacturing method of a multilayer printed wiring board in which a copper foil with carrier foil consists of at least four layers, a carrier foil/a release layer/a heat-resistant metal layer/a copper foil layer is used; a supporting substrate is manufactured by laminating an insulating layer constituting material on the surface of the copper foil layer constituting the copper foil with carrier foil; a supporting substrate with build-up wiring layer is manufactured by forming a build-up wiring layer on the surface of the carrier foil constituting the copper foil with carrier foil in the supporting substrate; the resulted supporting substrate with build-up wiring layer is separated at the release layer to manufacture a multilayered laminate; the resulted multilayered laminate is processed a necessary procedures to manufacture a multilayer printed wiring board.


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