The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Mar. 07, 2016
Applicant:
Fujitsu Limited, Kanagawa, JP;
Inventors:
Teru Nakanishi, Kawasaki, JP;
Nobuyuki Hayashi, Kawasaki, JP;
Masaru Morita, Kawasaki, JP;
Yasuhiro Yoneda, Kawasaki, JP;
Assignee:
FUJITSU LIMITED, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/02 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H05K 3/34 (2006.01); H05K 1/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0296 (2013.01); H01L 23/13 (2013.01); H01L 23/4985 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H05K 1/181 (2013.01); H05K 3/3436 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1379 (2013.01); H01L 2224/13839 (2013.01); H01L 2224/13847 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H05K 2201/10287 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10424 (2013.01); H05K 2201/10719 (2013.01); Y02P 70/613 (2015.11);
Abstract
A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.